1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of manufacturing a semiconductor device including a trench-type gate electrode.
2. Description of Related Art
In a semiconductor device, devices such as transistors are formed on a semiconductor substrate, so as to realize each function using the transistors. One of the transistors includes a power transistor that uses high current. In the power transistor, it is required to decrease a resistance value (on resistance) of the transistor in a conduction state and to use high current amount with low loss. In order to realize this object, a vertical structure which flows a current from a front surface of the substrate to a rear surface of the substrate is employed in the power transistor. One of the structures of the vertical transistor includes a trench gate structure. In the trench gate structure, a gate electrode is embedded in a groove (hereinafter referred to as trench) formed in the front surface of the semiconductor substrate and a channel is formed in a side wall of the trench. The transistor having the trench gate structure flows the current from a source region formed in the substrate surface to a drain region formed in the rear surface of the substrate through this channel.
One example of a semiconductor device having such a trench gate structure is disclosed in Japanese Unexamined Patent Application Publication No. 2001-284588. In the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2001-284588, a buried oxide film which is thicker than a gate oxide film formed in an inner wall of a trench is formed in a bottom part of the trench. Then, a diffusion region is formed that will be a channel region of a transistor using the buried oxide film as a mask by oblique ion implantation. As such, the impurity concentration of the diffusion region formed in the side surface of the trench is made uniform in the depth direction. By forming the channel region having uniform impurity concentration, a variation of a threshold voltage of the transistor is suppressed.
Further, in the semiconductor device, a device isolation region is provided in a substrate surface in order to electrically isolate the adjacent transistors. One example of the semiconductor device including the device isolation region is disclosed in Japanese Unexamined Patent Application Publication No. 8-293541. In the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 8-293541, the device isolation region separating the semiconductor substrate into an active region and an inactive region is disclosed. In the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 8-293541, an insulating film is buried in a trench, and a device isolation region including a region that is continuous with the trench is formed on the surface of the semiconductor substrate. As a result, according to the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 8-293541, the device isolation can be made possible without exposing the active region, thereby improving electrical characteristics of the device.